Currently, register renaming techniques employ a mechanism where the target register of an instruction is assigned a temporary rename buffer during the instruction dispatch cycle of that instruction. This instruction will hang on to the temporary buffer from the dispatch time until it is completed by the machine; which locks up rename resources for a long time (i.e. if the instruction is a load that misses L1 or L2 caches). A load miss in a cache is a typical event, for example, which looks up rename resources for a long time. Thus, a need exists for improved renaming.